SiFive is seeking a hardware design technical lead who is passionate about designing industry-leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating a highly customizable line of processor cores with fast time-to-market by designing the hardware as highly configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the speed and agility of software development. This role focused on debug, trace and profiling will be especially vital to SiFive’s effort to create silicon at the speed of software across our entire IP portfolio, including Essential, Intelligence, Performance, and Automotive product lines. We build and maintain our RISC-V processor subsystem IP using the Chisel hardware construction library embedded in the Scala language, and are seeking a motivated individual to lead enhancement of our existing debug/trace/profiling hardware as well as development of new capabilities in this area. Additionally, there are opportunities to engage with customer, partners and tools vendors to help determine the future of the debug, trace and profiling solutions, as well as opportunities to engage with the RISC-V International Association to help drive the state of the art of debug strategy. The successful applicant will address the following challenges: Designing the best debug, trace and profiling hardware in the world, based on the revolutionary open RISC-V and TileLink architectures. Mastering the art of designing hardware as configurable generators in a domain-specific software language for elaborating digital logic. Working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance. Join us, and surf the RISC-V wave with SiFive!