Lead ASIC Implementation Engineer, Amazon Leo's DBF Silicon

Amazon • San Diego, CA

4d

About The Position

Amazon Leo is Amazon’s low Earth orbit satellite network. Our mission is to
deliver fast, reliable internet connectivity to customers beyond the reach of
existing networks. From individual households to schools, hospitals, businesses,
and government agencies, Amazon Leo will serve people and organizations
operating in locations without reliable connectivity.

The Role:
Be part of Amazon Leo’s sub-team responsible for defining and implementing the
digital chip SOCs for communications via Low Earth Orbit satellites and Amazon
gateways. This is a unique opportunity to define a groundbreaking wireless
solution with few legacy constraints. The team works with customer requirements
and wireless system teams to define modems, high-speed interfaces, embedded
processors, and DSP solutions in latest CMOS generation technologies.

In this role you will:
• As the implementation lead you will set up the flow for both logic and
physical synthesis flow for various technology nodes.
• Work with the ASIC design and DFT teams to understand the design and create
timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks
are done properly and correct by construction, including formal connectivity
checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely
execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that
they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM
results.

Requirements

• Bachelor's degree in Electrical Engineering or a related field
• 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
• Experience leading or solely developing the methodology and scripts for physical synthesis.
• Proven track record in taping out chips that have gone in to high volume production.
• Familiar with implementing chips that have multiple power islands and power gating.

Nice To Haves

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• 10+ years of experience in ASIC implementation.
• Experience in leading physical design.
• Strong exposure to UPF flow for low power design.
• Strong written and verbal skills
• Experience of working in multi-site/multi-team environment

Responsibilities

• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level