Lead ASIC Design Engineer, Amazon LEO

Amazon.com, Inc.•Austin, TX

39d

About The Position

Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Be part of Amazon LEO's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

Requirements

8+ years of non-internship professional software development experience
8+ years of programming with at least one software programming language experience -
8+ years of leading design or architecture (design patterns, reliability and scaling) of new and existing systems experience
8+ years of digital design experience, preferably in SoC design and implementation
Fixed point RTL design
Filter design (FIR/IIR)
DSP design

Nice To Haves

5+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
Modem wireless or OFDM experience
Master's degree in computer science or equivalent

Responsibilities

RTL Design and development of custom blocks.
Integration of large subsystems
Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
Define, configure and integration SoC Subsystems
Contribute to the SoC floor planning effort
Define and develop any necessary support logic
Configure, instantiate and integrate 3rd party IP blocks
Understand low power design & the impact of DFT on the blocks
Perform initial synthesis & timing analysis
Assist verification team in unit verification including test plan development
Assist with debug and bring-up