Layout Design, Staff Engineer-10699

Synopsys • Sunnyvale, CA

254d • $134,000 - $201,000 • Onsite

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are an enthusiastic and detail-oriented Analog & Mixed-Signal (A&MS) Layout Design Engineer eager to make a significant impact in the field of semiconductor design. You have a strong foundation in Electrical Engineering, Computer Science, Physics, or a related discipline, with a keen interest in advanced process nodes and FinFET technology. Your analytical and problem-solving skills are exceptional, and you thrive in collaborative environments, effectively communicating with cross-functional teams. You are familiar with layout techniques, verification methodologies, EDA tools for layout design and verification. As a proactive and independent worker, you are also a team player, ready to engage with senior experts and contribute to innovative IP development.

Requirements

• Minimum of +10 years of related experience.
• Strong analytical and problem-solving skills.
• Excellent communication skills and ability to collaborate with cross-functional teams.
• Understanding of FinFET technology and advanced process nodes.
• Proficient with EDA tools for layout design and verification (DRC, LVS, etc).
• Strong working knowledge of MS Office Suite of applications.
• Familiarity with Python, Tcl, SKILL or other scripting language for layout automation is a plus.
• Proficiency in verbal and written English to collaborate effectively with global teams.
• Ability to work independently while collaborating effectively within a team.

Nice To Haves

• Familiarity with Python, Tcl, SKILL or other scripting language for layout automation.

Responsibilities

• Designing and developing analog and mixed-signal layouts for OTP (One Time Programmable) memory IP in the latest technology nodes.
• Collaborating with cross-functional teams to meet project requirements and deadlines.
• Debugging and resolving a wide range of issues in creative ways.
• Utilizing EDA tools for layout design, verification, and ensuring compliance with DRC, LVS, ERC, and PERC methodologies.
• Working closely with our memory architect to floorplan and develop leading edge memory architecture.
• Executing layout projects under the guidance of layout and design leads contributing to memory IP development.

Benefits

• Comprehensive health, wellness, and financial benefits.
• Annual bonus eligibility.
• Equity and other discretionary bonuses.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Publishing Industries
• Education Level: Bachelor's degree