IP EDA Verification & Automation Engineer

ARM-posted 3 months ago
$241,100 - $326,100/Yr
Full-time • Senior
Hybrid • Austin, TX
5,001-10,000 employees
Professional, Scientific, and Technical Services
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Arm teams develop groundbreaking Silicon demonstrators which embeds the latest Arm Compute Sub-System IP (Intellectual Property) and other various outsourced IP. We are looking for a creative and hardworking principal engineer to join the IP Qualification team to verify these Third-Party IPs before they are embedded in SoC. Such TPIP are foundation IP (e.g. standard-cells, SRAM), NVM (e-fuse, anti-fuse), PLL, sensors, as well as sub-system Interfaces (controller + PHY) like LPDDR, USB, Ethernet or PCIe. You will join a newly formed team in Austin as well as collaborate with multiple other groups inside of Arm.

  • Lead the installation and the verification of all the TPIP EDA models for Silicon demonstrators.
  • Ensure compliance with Arm SoC design flow requirements and DFX requirements.
  • Use the IP Qualification flow along with EDA tools from major providers.
  • Analyze deviations and share them with SoC design teams for review.
  • Report deviations to the IP providers for updates.
  • Propose and lead the implementation of new checks to improve coverage and compliance.
  • At least 15 years of post-master degree work experience in IP design or verification and/or implementation and signoff.
  • Functional verification of IP blocks/subsystems.
  • RTL code Linting and CDC/RDC verification.
  • Scan stitching, ATPG and patterns simulation.
  • Synthesis, low-power (UPF) physical implementation and verification, timing and power signoff.
  • Power grid integrity (electro-migration, voltage-drop) and physical checks.
  • Scripting for tasks automation with Shells (e.g. Bash), TCL, Python or any other language.
  • Excellent interpersonal skills, strong initiative and open in engaging and learning various IP and the SoC reference design flow.
  • Experience in Verify-IP usage for Interface IP protocol verification.
  • Boundary scan integration (IEEE-1149).
  • SI/PI (signal/power integrity) checks at chip/package level.
  • Functional Safety and Cyber Security requirements.
  • Private medical insurance (employee and family).
  • 20 days annual leave.
  • 20-day sabbatical every four years.
  • Supplementary pension.
  • Reduction in working hours.
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