IP Design Verification Engineer

Intel-posted 3 months ago

$153,540 - $216,770/Yr

Full-time • Mid Level

Santa Clara, CA

5,001-10,000 employees

Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services

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This position is with the server group at Intel. This team is central team responsible for developing and delivering Verification IPs to server group. The position involves leading functional verification of IP logic blocks to ensure design compliance with specification requirements, driving comprehensive verification methodologies from planning through silicon validation.

Develop functional Verification IPs targeted for simulation and emulation testbench environments
Perform functional verification of IP logic to ensure designs meet specification requirements and microarchitecture standards
Develop comprehensive IP verification plans, test benches, and verification environments with full coverage analysis
Execute verification plans and define system simulation and emulation models to verify design functionality and identify design issues
Replicate, root cause, and debug issues in pre-silicon environments using advanced debugging methodologies
Identify and implement corrective measures to resolve failing tests and improve overall design quality
Collaborate with architects, RTL developers, and physical design teams to enhance verification of complex architectural and microarchitectural features
Document detailed test plans and lead technical reviews with design and architecture teams to ensure verification completeness
Maintain and continuously improve existing functional verification infrastructure, methodologies, and best practices
Participate in defining verification infrastructure requirements and related Test Flow Methodologies (TFMs) for functional design verification
Drive verification closure through systematic coverage analysis and regression testing protocols

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or related field with 6+ years of experience -OR- Master's degree in Computer Engineering, Computer Science, Electrical Engineering or related field with 4+ years of experience
C/C++ programming and Object-Oriented Software design, including algorithms and data structures
Software development practices and quality standards
Experience with Unix/Windows-based software development tools
Experience developing bus functional models for unit-level verification or Verification IP development

Proficiency in SystemC, SystemVerilog, UVM, and ESL modeling methodologies
Proficiency in hardware design and verification methodologies
Working knowledge of high-speed hardware protocols (e.g., PCIe, UPI, DDR)

Competitive pay
Stock options
Bonuses
Health benefits
Retirement plans
Vacation

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