Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Our Link Design and Architecture team is responsible for ensuring the robustness and performance of the optical links that power our technology. We are seeking a highly motivated graduate intern to join our Link Design team and help shape our silicon photonics optical I/O platform. In this role, you will contribute to the architectural vision by helping to develop advanced models that unify electrical circuits and photonic devices. By capturing signal processing and physical behavior, you will assist in optimizing the performance of Ayar Labs' co-packaged optics (CPO) solution. Furthermore, you will evaluate test data to calibrate these models and drive meaningful design improvements. The projects are tailored to your experience and interests, and you will be mentored by a senior engineer as you work alongside Ayar Labs engineers to help drive the optical I/O revolution.
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Career Level
Intern