Intern - Engineering (ASIC Physical Design)

Microchip • San Jose, CA

16d • $19 - $30 • Onsite

About The Position

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Microchip Technology Inc. has an ASIC Physical Design Internship opening based in San Jose, CA. As a member of Microchip’s engineering community, you will collaborate closely with the chip design team to support ASIC backend flow, including place and route (P&R), timing/noise/power signoff, as well as the integration of multiple blocks within the FPGA.

Requirements

• Currently pursuing a Bachelors or Master’s degree in Computer Science, Electrical Engineering, or a related field.
• Demonstrated knowledge of digital Design fundamentals and semiconductor principles through course work or previous internships.

Nice To Haves

• Prior experience with IC digital implementation flows and backend EDA tools, including Place and Route, IR drop analysis, and design timing and power closure, is preferred.
• Proficiency in scripting languages such as Tcl, Perl or Python is highly beneficial.

Responsibilities

• Work as part of a team of experienced design engineers supporting backend ASIC implementation, including place and route, design closure, and timing/power signoff.
• Collaborate closely with the digital design, verification, and analog teams to ensure all components are thoroughly verified and successfully integrated into the FPGA.
• Partner with the design team to conduct technical presentations.
• Customize, automate and enhance the design flow as needed using Tcl/Python.

What This Job Offers

• Career Level: Intern
• Number of Employees: 5,001-10,000 employees