Intern - Analog Layout
About The Position
As a Layout Designer, the candidate will work closely with Microchip’s Engineering Services team to complete analog layout tasks of integrated circuits for world-wide design teams. As an intern level candidate, he/she will: Train in the art of analog layout of CMOS and FinFet integrated circuits Learn the Cadence IC Layout tools and Mentor Calibre Physical verification tools Learn layout methodologies focused on custom analog layout principles Complete cell layouts of varying complexity under the guidance of a senior layout engineer Utilize design collaboration tools with local and world-wide teams Work on a computer workstation daily in the Linux OS environment
Requirements
- AS or BS degree majoring in Electronic Engineering Technology, Electronic Mechanical Engineering Technology, or related program with interest in the IC semiconductor industry
- Completed one course in Semiconductor Design, IC Wafer Fabrication Theory, or related studies
- Interest in the IC semiconductor industry
- Must have a minimum 2.8 GPA
- Excellent organizational skills and detail oriented
- Good communication skills, great work ethic, and the desire to continually learn
- Microsoft Office skills with focus in Excel and Word
Responsibilities
- Train in the art of analog layout of CMOS and FinFet integrated circuits
- Learn the Cadence IC Layout tools and Mentor Calibre Physical verification tools
- Learn layout methodologies focused on custom analog layout principles
- Complete cell layouts of varying complexity under the guidance of a senior layout engineer
- Utilize design collaboration tools with local and world-wide teams
- Work on a computer workstation daily in the Linux OS environment
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What This Job Offers
Career Level
Intern
Education Level
Associate degree
