Broadcom-posted 5 days ago
Full-time • Mid Level
San Jose, CA
5,001-10,000 employees

Job duties include: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Work with other members of the team, guide/mentor junior team members Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Driver Verification quality and Efficiency improvements

  • Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
  • Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
  • Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
  • Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
  • Work with other members of the team, guide/mentor junior team members
  • Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
  • Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc.
  • Lead reviews with design/architecture.
  • Driver Verification quality and Efficiency improvements
  • Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience of Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience
  • 10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
  • Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
  • Very proficient in System Verilog and Verification Methodologies like UVM/VMM
  • Good debug skills in analyzing regression failures and understanding of complex designs
  • A good understanding of a complex protocol like PCI Express or other multi-layered protocol
  • Work with the team and mentor junior engineers
  • Experience in PCIe protocol
  • Scripting knowledge of Python or Perl
  • Comfort with Makefiles
  • Experience with Verifying with other protocols like AXI
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company paid holidays
  • paid sick leave and vacation time
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