Astera Labs-posted 7 months ago
Senior
Santa Clara, CA
251-500 employees

We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D packaging, signal and power integrity (SIPI), and chiplet technology, as well as experience scaling technologies to high-volume manufacturing. This role demands a deep understanding of advanced packaging architectures (such as CoWoS, interposers, WLP, and heterogeneous/chiplet integration) alongside strong expertise in SI and PI. The successful candidate will contribute to strategic roadmap execution and deliver package solutions into production.

  • Lead and innovate in the development of high-performance IC package solutions.
  • Contribute to strategic roadmap execution and deliver package solutions into production.
  • Engage with foundries, OSATs, and substrate suppliers for collaborative package technology development.
  • Demonstrate success in leading die-package-board co-design efforts.
  • Optimize signal and power integrity (SIPI) for ultra-high-speed interfaces.
  • Conduct hands-on lab validation and simulation-correlation with high-frequency measurement.
  • M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.
  • 10 years of experience in IC packaging development with deep exposure to SIPI and 2.5D/3D integration technologies.
  • Hands-on experience with CoWoS, interposers, WLP, chiplet-based integration.
  • Proficiency in SIPI tools: HFSS, Siwave, ADS, HSPICE, etc.
  • Hands-on experience in high-frequency measurement and characterization with VNA.
  • Expert knowledge of EDA design tools: Cadence Allegro/APD, Altium, etc.
  • Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing engineering teams.
  • Knowledge of mechanical, thermal, and electrical design trade-offs in package development.
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