IC Package Design Engineer

Red Cell Partners • Torrance, CA

20h • $155,000 - $190,000 • Hybrid

About The Position

Claros Technologies is seeking an IC Package Layout Engineer to design, develop, and optimize advanced IC package substrates for high-performance semiconductor products. This role involves close collaboration with IC design, system, SI/PI, thermal, and manufacturing teams to deliver robust, manufacturable package solutions that meet stringent electrical, mechanical, and reliability requirements.
The ideal candidate brings strong experience in full-package layout, high-speed interface support, DFM/DRC compliance, and documentation for production release.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 6-8 years overall experience in IC package layout and substrate design.
• Proficiency with Cadence Allegro Package Designer (APD).
• Solid understanding of SI/PI fundamentals, stack-up design, and package-level constraints.
• Hands-on experience with BGA packaging, ball map creation, and full-package routing.
• Familiarity with DRC/DFM processes and manufacturing requirements.
• Experience using Cam350 and AutoCAD for layout verification and documentation.
• Strong communication skills and ability to work effectively with cross-functional engineering teams.

Nice To Haves

• Experience supporting high-performance networking, switching, optical, or processor products.
• Exposure to SI/PI or thermal simulation workflows and design reviews.
• Familiarity with package assembly flows and global manufacturing operations.
• Experience working in large-scale semiconductor environments.

Responsibilities

• Design and route complete IC packages, including stack-up definition, signal routing, power distribution, and optimization for SI/PI performance.
• Analyze die floorplans, develop ball maps, perform fan-out studies, and assess routing feasibility to ensure optimal package performance and reliability.
• Apply knowledge of high-speed interfaces (e.g., DDR, PCIe, USB, FPGA, RGMII, GPIO) to support high-bandwidth and low-latency designs.
• Navigate complex design constraints and incorporate simulation and design review feedback to improve electrical and manufacturing outcomes.
• Perform DRC and DFM checks using tools such as Cam350, ensuring compliance with industry and foundry standards.
• Create accurate substrate drawings, bonding diagrams, and manufacturing deliverables using AutoCAD.
• Define BGA ball patterns and optimize routing in collaboration with chip and package engineers.
• Generate and maintain package design documentation, assembly instructions, and build sheets using Oracle PLM or equivalent systems.
• Support package design and assembly documentation for multiple product lines, coordinating with global operations and manufacturing teams.
• Work cross-functionally with IC design, system architecture, SI/PI, thermal, and package assembly teams using Cadence APD (v17.x).

Benefits

• Career track opportunity with potential for rapid advancement with strong performance as the firm grows
• 100% employer paid, comprehensive health care including medical, dental, and vision for you and your family.
• Paid maternity and paternity for 14 weeks at employees' normal pay.
• Unlimited PTO, with management approval.
• Opportunities for professional development and continued learning.
• Optional 401K, FSA, and equity incentives available.
• Salary Range: $155,000-$190,000. This represents the typical salary range for this position based on experience, skills, and other factors.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 51-100 employees