IC Layout designer
About The Position
Responsibilities: Delivering the entire chip layout to the committed timeframe and within the required design requirements. Being responsible for the entire chip Tapeout and physical verification. Complete layout and verification of analogue and mixed-signal designs using industry-standard CAD tools. Be responsible for floor planning, custom layout and verifying against design rules. Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. Ability to solve layout design problems and provide innovative solutions. Contribute to complex IC development projects and prepare documents for knowledge sharing. Proven record of completing tasks on time or ahead of schedule while maintaining quality. Qualifications: Minimum of 10 years of relevant mask design/layout experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration. Must have experience in handling full chip layout and integration using state-of-the-art IC layout tools like Cadence Virtuoso. Must have experience with FINFET process. Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. Experience with EM & IR Analysis and fixing for the layout closure. Experience in DRC, LVS, ERC, Antenna, and post layout extraction using Pegasus/Calibre verification tools. Knowledge of foundry command deck, PDK, fabrication & mask process. Must have design management techniques to ensure quality and deliver on schedule.
Requirements
- Minimum of 10 years of relevant mask design/layout experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration.
- Must have experience in handling full chip layout and integration using state-of-the-art IC layout tools like Cadence Virtuoso.
- Must have experience with FINFET process.
- Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc.
- Experience with EM & IR Analysis and fixing for the layout closure.
- Experience in DRC, LVS, ERC, Antenna, and post layout extraction using Pegasus/Calibre verification tools.
- Knowledge of foundry command deck, PDK, fabrication & mask process.
- Must have design management techniques to ensure quality and deliver on schedule.
Responsibilities
- Delivering the entire chip layout to the committed timeframe and within the required design requirements.
- Being responsible for the entire chip Tapeout and physical verification.
- Complete layout and verification of analogue and mixed-signal designs using industry-standard CAD tools.
- Be responsible for floor planning, custom layout and verifying against design rules.
- Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs.
- Ability to solve layout design problems and provide innovative solutions.
- Contribute to complex IC development projects and prepare documents for knowledge sharing.
- Proven record of completing tasks on time or ahead of schedule while maintaining quality.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
11-50 employees
