IC Design Engineer

Broadcom Corporation • San Jose, CA

37d

About The Position

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture definition Perform RTL design using Verilog HDL, with an emphasis on performance and area Implement multi-power and low-power designs Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design Collaborate with verification team on test plan development, debugging, and coverage closure Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks using UPF/CPF flows and ECO implementation. Support system level validation efforts on FPGA/emulation Support silicon bring-up and debug efforts

Requirements

• BS+12 Years of relevant industry experience. Advanced degree preferred
• Must have strong Logic Design, RTL coding (Verilog HDL) and debugging skills
• Must have an understanding of low power design and validation techniques including UPF/CPF
• Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks
• Must be able to assist in silicon and FPGA debug and bring-up
• Self-motivated
• Ability to work independently
• Good verbal and written communication skills
• Ability to work with remote and cross functional teams

Nice To Haves

• ARM CPUs
• Memory controllers
• Peripherals such as I2C, SPI and UART
• Peripherals and interconnect protocols such as APB, AHB and AXI
• Digital Signal Processing designs, usage of Matlab and Simulink
• Scripting languages such as (Python perl/tcl)
• Mixed signal design

Responsibilities

• Participate in IP level architectural definition including micro-architecture definition
• Perform RTL design using Verilog HDL, with an emphasis on performance and area
• Implement multi-power and low-power designs
• Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design
• Collaborate with verification team on test plan development, debugging, and coverage closure
• Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks using UPF/CPF flows and ECO implementation.
• Support system level validation efforts on FPGA/emulation
• Support silicon bring-up and debug efforts

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees