I/O Modeling and Characterization Engineer

Qualcomm-posted 3 months ago
$98,500 - $147,700/Yr
San Diego, CA
Computer and Electronic Product Manufacturing
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This is a I/O modeling and characterization lead position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products.

  • Architect and oversee the development of RTL models in Verilog for various IO configurations, ensuring scalability, reusability, and alignment with system-level requirements.
  • Define and drive the verification strategy, including planning, execution, and sign-off for both behavioral and transistor-level implementations.
  • Ensure comprehensive coverage and alignment with project milestones.
  • Lead the adoption and integration of advanced verification methodologies, including SystemVerilog Assertions (SVA), power-aware verification, and formal verification techniques collaborating with cross-functional teams to resolve complex issues efficiently.
  • Demonstrate expertise in VLSI circuit design, with hands-on experience in SPICE simulations and commercial characterization tools.
  • Drive best practices across the team.
  • Review and guide the development of stimulus for timing and power characterization, ensuring alignment with I/O circuit architecture and performance targets.
  • Ensure accurate modeling and interpretation of Liberty formats including NLDM, CCS, and LVF.
  • Provide guidance on model generation and validation.
  • Champion automation initiatives using scripting languages such as Python, Perl, or TCL to enhance productivity, consistency, and quality across the design and verification flows.
  • Collaborate closely with internal stakeholders, including SoC teams, to gather requirements and deliver high-quality behavioral and timing models throughout the design lifecycle.
  • Engage with EDA tool vendors to influence tool development and drive methodology improvements aligned with requirements of a cutting-edge technology nodes.
  • Bachelor's degree in Science, Engineering, or related field.
  • 0 - 3 years of experience in RTL coding, Verilog and System Verilog Test benches, Design verification, IP characterization or related work experience.
  • 0 - 3 years of experience in flow development with scripting tools and programming languages.
  • Master's degree in electrical engineering.
  • $98,500.00 - $147,700.00 salary range.
  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support success at work, at home, and at play.
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