HW SOC/ASIC Physical Design Engineer, Principal

Qualcomm • San Diego, CA

67d • $192,000 - $288,000

About The Position

We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low-skew, power-efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full-time onsite work in San Diego, CA (5 days per week).

Requirements

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• 10+ years of experience in physical design, with a focus on clock tree design and implementation.
• Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.
• Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime).
• Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
• Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis.

Nice To Haves

• Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies.
• Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling.
• Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe).
• Understanding of package-level clock planning and signal integrity.

Responsibilities

• Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2).
• Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime).
• Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
• Optimize design for power, performance, and area (PPA).
• Conduct formal equivalence checks between RTL and netlist.
• Support physical verification including DRC, LVS, and antenna checks.
• Work closely with backend teams for tapeout preparation and signoff.
• Develop and maintain automation scripts for verification flows, reporting, and regression testing.
• Interface with EDA vendors to resolve tool issues and improve flow robustness.
• Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability.
• Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree