HW Design Verification Intern

d-Matrix • Santa Clara, CA

1d • Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
You will work alongside a team building state-of-the-art LLM inference SoCs, gaining hands-on exposure to modern compute units, crossbars, chiplet interconnects, and high-performance memory interfaces.
In this role,
You’ll contribute to the functional verification of complex hardware blocks using UVM-based methodologies and
Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA).
You’ll also develop and maintain tools that improve simulation efficiency and verification productivity, and
Help explore how emerging AI-assisted workflows can strengthen DV methodology.

Requirements

• Pursuing a Master’s or PhD degree in Electrical and Computer Engineering, or a related scientific discipline
• Relevant coursework in Computer Architecture, Verilog, and/or FPGA development
• Familiarity with the SystemVerilog programming language (required)
• Excellent verbal and written communication skills

Nice To Haves

• Familiarity with SystemVerilog Assertions (SVA) (preferred, not required)
• Current knowledge of AI SoC and/or LLM inference architectures (preferred, not required)

Responsibilities

• Contribute to the functional verification of complex hardware blocks using UVM-based methodologies
• Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA)
• Develop and maintain tools that improve simulation efficiency and verification productivity
• Help explore how emerging AI-assisted workflows can strengthen DV methodology

What This Job Offers

• Career Level: Intern