HSIO Functional Validation Engineer

Nvidia • Santa Clara, CA

90d • $168,000 - $264,500

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. NVIDIA's High-Speed Interconnect (HSIC) team is seeking a versatile engineer to be part of a Silicon Hardware team. You will dive into next-gen high speed interconnects like NVLink and NVLink-C2C to make advancements in efficiency and stability. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from artificial intelligence, consumer graphics, self-driving cars, and more.

Requirements

• BS or MS degree in EE/CE or equivalent experience.
• 8+ years working on bringup, validation, or design of HSIOs (eg: PCIE/CXL, DDR, USB, UCIE).
• Experience with HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity.
• Understanding of HSIO power management.
• Understanding of firmware/driver structures and their interaction with Hardware.
• Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis.
• Enjoy working in a collaborative environment.

Responsibilities

• Silicon bringup, validation, and debug NVIDIA's multiple HSIOs, including NVLink and NVLink-C2C.
• Own the post-silicon electrical validation of Chip-to-Chip (C2C) and NVLink high-speed interfaces across multiple product lines (GPU, CPU, DPU, SoC).
• Develop validation plans, test methodologies, and automation frameworks for link bring-up, margining, and compliance.
• Execute validation of signal integrity (SI), power integrity (PI), timing margins, equalization tuning, and error metrics across PCIe Gen5/Gen6, C2C, and NVLink interconnects.
• Debug link-level and system-level electrical issues including jitter, crosstalk, transient noise, BER, and channel loss problems.
• Collaborate closely with design, architecture, system, and SI/PI teams to ensure robust interface design and production-level performance.
• Characterize link health under PVT (process, voltage, temperature) corners and stress conditions to ensure product reliability.
• Deliver data analysis, reports, and recommendations to influence design decisions and drive issue resolution.
• Investigate HSIO power features, datapath analysis, and electrical for the next generation of products.
• Power feature char and tuning for key use cases, balancing performance and power.

Benefits

• Competitive salaries
• Generous benefits package
• Equity opportunities

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree