High Speed Serdes System Design Engineer

Broadcom

5d

About The Position

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+. The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities. You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production. You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF.

Requirements

• B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required)
• Expert knowledge in Communication Theory
• Expert knowledge in Digital Signal Processing algorithms
• Working knowledge of Analog circuit behavior
• Working knowledge of Transmission line theory and s-parameter
• Expert in MATLAB, C/C++ programming
• Good hands-on skills in the lab

Nice To Haves

• Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
• Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.
• RTL coding is a plus
• Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus

Responsibilities

• Develop channel models and run simulations to help define Serdes architecture
• Define and document signal processing block requirements, architecture, and lab test plan
• Develop bit-exact MATLAB and C/C++ system models for simulation and verification
• Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs
• Work with the design team to perform vector matching verification with RTL simulations
• Develop, test, and debug firmware associated with physical layer functionality
• Lab testing and debug of Serdes
• Documentation/application note development and customer support
• Support marketing group with customer meetings and collateral

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees