Broadcom is looking for a high-speed DSP SerDes RTL designer. The ideal candidate will have a strong background in Electrical Engineering or Computer Engineering, with a focus on high-speed ADC based SerDes RTL design. This role requires proficiency in Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes, including equalization, adaptation, and high-speed ADC calibration. The candidate should also be familiar with front-end tools such as NCVerilog, NCSIM, Simvision, and Lint. Additionally, exposure to Design for Test (DFT) concepts and writing DFT friendly RTL is essential. A deep understanding of high-speed serial interconnect architectures, such as 100G/200G per lane PAM4, is necessary to drive performance, power, and cost metrics throughout the project lifecycle. Experience in synthesis, CDC, static timing analysis, and SDF annotated simulations is also required. The candidate should possess strong analytical thinking and problem-solving skills, be organized, self-motivated, and able to work effectively across internal and end customer teams. Knowledge of TSMC 7nm-2nm technology, including power consumption, area, and design/layout efforts for digital and analog blocks, is crucial.