High Speed SerDes DSP RTL Designer

Broadcom-posted 2 months ago

$120,000 - $192,000/Yr

Full-time • Mid Level

San Jose, CA

5,001-10,000 employees

Computer and Electronic Product Manufacturing

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Broadcom is looking for a high-speed DSP SerDes RTL designer. The ideal candidate will have a strong background in high-speed ADC based SerDes RTL design, with a focus on Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes. The role requires proficiency in front end tools and a deep understanding of high-speed serial interconnect architectures. The candidate should also have experience in design management and a strong analytical mindset.

Design high-speed ADC based SerDes RTL.
Code in Verilog-HDL/System Verilog for PAM4 DSP based SerDes including equalization, adaptation, and high-speed ADC calibration.
Utilize front end tools such as NCVerilog, NCSIM, Simvision, and Lint.
Implement Design for Test (DFT) concepts and write DFT friendly RTL.
Analyze high-speed serial interconnect architectures and make design trade-offs.
Conduct synthesis, CDC, and static timing analysis.
Perform SDF annotated simulations and understand parasitic delays.
Manage design processes with knowledge of development methodologies and EDA integration.

MS or PhD in Electrical Engineering or Computer Engineering.
6+ years of experience in high-speed ADC based SerDes RTL design.
Proficient in Verilog-HDL/System Verilog coding.
Experience with front end tools like NCVerilog, NCSIM, Simvision, and Lint.
Understanding of Design for Test (DFT) concepts.
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4.
Experience in synthesis, CDC, and static timing analysis.
Knowledge of SDF annotated simulations and parasitic delays.
Experience in design management and EDA integration.
Strong analytical thinking and problem-solving skills.
Excellent organizational and self-motivational skills.

Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
Exposure to Verilog AMS simulation and experience in behavioral models of analog circuits.

Medical, dental and vision plans.
401(K) participation including company matching.
Employee Stock Purchase Program (ESPP).
Employee Assistance Program (EAP).
Company paid holidays.
Paid sick leave and vacation time.

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