High-speed Interface Micro Architect and RTL Design Engineer

Qualcomm • San Diego, CA

69d • $164,000 - $246,000 • Remote

About The Position

The Mixed-Signal IP team at Qualcomm is seeking skilled digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs-including SerDes, DDR, and die-to-die interconnects-for integration across Qualcomm's product portfolio. In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as SerDes, DDR, PLLs, DACs, ADCs, and sensors
• Proficiency with industry-standard ASIC design tools including Design Compiler, PrimeTime, Power Compiler (PTPX), VCS, DFT Compiler, Spyglass, and others

Nice To Haves

• Ph.D. in Electrical Engineering with 3+ years of industry experience in high-speed digital circuit design
• Strong background in low-power digital design techniques
• Expertise in computer architecture, digital signal processing, and algorithm development
• Experience developing automation scripts and design productivity tools using Python or Perl

Responsibilities

• Architect and define the digital design of high-speed interface IPs (e.g., SerDes, DDR, die-to-die) in close collaboration with system architecture and analog teams
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
• Design and analyze DFT logic, including ATPG for stuck-at fault (SAF) and transition delay fault (TDF) coverage
• Create comprehensive design documentation, including hardware specifications
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
• Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
• Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up

Benefits

• $164,000.00 - $246,000.00 salary range
• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees