High-Speed Analog/Mixed-Signal Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

1d•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Be part of AMD’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, chip-to-chip,…) and chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include THE PERSON: The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills.

Requirements

BS, MS or PhD in in Electrical Engineering, Computer Engineering or related equivalent

Nice To Haves

Experience in high speed serial and/or parallel mixed signal PHY/IO designs
Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking.
Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs such as UCIe.
Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, …
Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off
Solid understanding of power, area and performance trade-offs in mixed signal IP design
Design Experience in FinFet advanced CMOS process nodes 7nm and below coupled with a solid understanding of transistor device performance and fundamentals
Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements
Track record of successfully taking designs to production
Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment.
Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge

Responsibilities

Definition, review and sign-off on IP top level and component level specifications
AMS components circuit and layout design
Supervise pre-silicon layout, post-silicon characterization and debug.
Support product bring-up and debug , and Sign-off on test-plans and characterization reports.
Interface with SOC teams, system HW/SW teams, and global manufacturing teams.