Head of Design Verification, Interface IP

Etched • San Jose, CA

8d • $200,000 - $300,000 • Onsite

About The Position

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. This is a hands-on technical leadership role: you will manage a small team while personally owning DV strategy, execution, and tape-out sign-off for critical subsystems including CPU subsystems, HBM memory controllers, PCIe, Ethernet, and system peripherals.
You will lead Interface IP DV from architecture definition through tape-out, working closely with RTL designers, IP vendors, SoC and performance DV, software, and architecture teams. You will set standards, define best practices, and ensure verification quality scales with increasingly ambitious chips.

Requirements

• 10+ years of design verification experience with ownership of complex IP or SoC subsystems
• Deep hands-on expertise in SystemVerilog and UVM
• Strong understanding of SoC mCPU design and high-speed interfaces (PCIe, Ethernet, AXI/AMBA)
• Tape-out experience with final DV sign-off responsibility
• Systems-level DV mindset
• Comfortable being hands-on in a fast-moving startup environment

Nice To Haves

• Experience leading DV teams at Apple, NVIDIA, Broadcom, AMD, or similar
• Vendor IP evaluation and integration experience
• Exposure to formal verification, emulation, or silicon bring-up
• Power-aware or low-power interface verification

Responsibilities

• Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs
• Act as the technical authority on correctness, protocol compliance, performance, and robustness
• Lead DV for CPU subsystems (boot, interrupts, coherency, system control)
• Lead DV for high-speed interfaces, including throughput and latency verification
• Architect and evolve SystemVerilog/UVM verification environments
• Drive vendor IP integration, configuration reviews, and verification gap closure
• Partner closely with architecture, RTL, SoC DV, and software teams
• Hire, mentor, and lead a small, high-impact Interface IP DV team
• Advise the strategy and execution of emulation testing for pre-silicon validation

Benefits

• Full medical, dental, and vision packages, with generous premium coverage
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to San Jose (Santana Row)

What This Job Offers

• Job Type: Full-time
• Career Level: Executive
• Education Level: No Education Listed
• Number of Employees: 101-250 employees