HBM SOC Design Engineer

Micron Technology-posted 2 months ago
Full-time • Mid Level
Richardson, TX
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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As an HBM SOC Design Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target best-in-class performance, power, cost, reliability and quality for Micron's HBM product portfolio.

  • Analyze customer requirements and specification documents, work with IP vendors to select off-the-shelf IPs, and modify or custom design new ones if needed.
  • Review architectural specifications and provide constructive feedback to help create high-quality specifications.
  • Writing specifications, developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static checks.
  • Proactively identify and flag quality issues, performance problems, and opportunities to reduce power consumption in architecture, microarchitecture, RTL, or circuits.
  • Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.
  • 3+ years of relevant job/skill-related experience.
  • Proficiency in microarchitecture and high-quality RTL development with the ability to write and test code in System Verilog.
  • Experience dealing with clock domain crossings (CDC), static timing analysis, synthesis design constraints, and closing timing by using logic techniques, false path constraints, and multi-cycle path constraints.
  • Experience with SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc.
  • Understanding of design for testability concepts such as MBIST and scan and how to write RTL for testability.
  • BSEE or higher with a track record of innovation and problem-solving in high-performance and/or low power SOC development.
  • Familiarity with scripting languages such as Python.
  • Experience with working on one or more of the following IPs: UCIE, Memory Controller, NOCs.
  • The ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership.
  • A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds.
  • Choice of medical, dental and vision plans.
  • Benefit programs that help protect your income if you are unable to work due to illness or injury.
  • Paid family leave.
  • Robust paid time-off program.
  • Paid holidays.
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