HBM Memory Subsystem Architect – Principal Engineer
About The Position
Develop innovative memory subsystem architectures for HBM-based AI/ML solutions, including PHY, memory controllers, NOC, microcontrollers, MBIST, interfaces, adapters, RAS, and support for DDR/LPDDR/HBM memory types. Define Memory and RAS architecture requirements and drive end‑to-end architectural specification for next‑generation memory subsystems. Collaborate with internal and external partners to develop novel architectures and detailed IP requirements across all memory subsystem components. Lead engagement with IP vendors, including evaluation and selection of interface IP and functional IP blocks. Analyze benchmarks, workloads, and simulation results to identify performance and efficiency innovation opportunities in memory subsystems. Perform performance and performance/Watt modeling; estimate gate count, power, and area; and generate architectural and external-facing specifications aligned with hardware/protocol standards. Partner with RTL, validation, and multi-functional teams to ensure successful and timely implementation of subsystem features, contributing to technical reviews for HBM and memory products. Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across high‑level models, RTL simulation, and hard/soft IP.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Minimum of 10 years of experience in memory subsystem architecture and design
- Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
- Experience with PHY design and understanding of signal integrity issues
- Proficiency in Network-on-Chip (NoC) architecture and design
- Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc
- Strong analytical and problem-solving skills
- Excellent written and verbal communication skills
Nice To Haves
- A PhD in a relevant field, or equivalent experience
- Familiarity with EDA tools for design and verification
- Practical experience with multi-core systems, coherent interconnects & Industry IO protocol like PCIe/CXL, confidential compute, virtualization & security
- Knowledge of serial link protocols (UCIe etc.) is desired
Responsibilities
- Develop innovative memory subsystem architectures for HBM-based AI/ML solutions
- Define Memory and RAS architecture requirements
- Drive end‑to-end architectural specification for next‑generation memory subsystems
- Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
- Lead engagement with IP vendors, including evaluation and selection of interface IP and functional IP blocks
- Analyze benchmarks, workloads, and simulation results to identify performance and efficiency innovation opportunities in memory subsystems
- Perform performance and performance/Watt modeling; estimate gate count, power, and area; and generate architectural and external-facing specifications aligned with hardware/protocol standards
- Partner with RTL, validation, and multi-functional teams to ensure successful and timely implementation of subsystem features, contributing to technical reviews for HBM and memory products
- Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across high‑level models, RTL simulation, and hard/soft IP
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What This Job Offers
Career Level
Principal
