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As a Hardware Power Test Engineering Manager at Google, you will be part of a diverse team that is dedicated to pushing the boundaries of technology by developing custom silicon solutions that power the future of Google's direct-to-consumer products. Your role will involve managing a team of hardware test engineers who are responsible for participating in hardware design reviews and performing onboard power validation. You will act as a liaison between hardware engineering teams and the lab team, ensuring that lab resources are accounted for and that the team is prepared for new products entering the labs or sustaining efforts. This position is crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration in products that are loved by millions worldwide. In this role, you will define, execute, and document the electrical characterization, validation, and qualification of the on-board system-level power distribution network (PDN). This encompasses everything from the DC-DC power converter design to ASIC power integrity validation. You will drive improvements in power measurement methodologies, test automation, and processes across compute and machine learning products. Additionally, you will support design engineers with debugging, component validation, and failure analysis of released products. Your expertise will be instrumental in collecting and analyzing aggregated data to enable data-driven engineering decisions, reporting on findings, reducing test data, and investigating test outcomes at a hardware interface or component level. You will collaborate with hardware designers and other diagnostics development teams to understand new project power distribution architectures and system test requirements, which will help in developing resource requirements for the team.
