Graduate - Analog, Mixed Signal Verification Engineer
About The Position
In your new role you will: Verification Leadership: Drive the verification of mixed-signal ICs using best practices to ensure first-pass silicon success Model Creation: Create and verify block-level models (e.g., System Verilog, VAMS) for use in top-level mixed-mode simulations Test Development: Develop application-specific test benches with automated checkers to evaluate IC functionality and robustness Collaboration: Work closely with application, analog design, and digital design leads to verify system-level and IC-level functions and specifications Debug Support: Partner with the design team to analyze and address errors found during the verification process Team Culture: Foster a collaborative, innovative, and resilient team culture that encourages open communication Target Start Date: Summer 2026
Requirements
- Graduating in the spring of 2026 with a Bachelor’s or Master’s degree in Electrical Engineering or a related field
- Experience in analog or mixed-signal design verification, with proficiency in UVM-based methodologies
- Skilled in modeling analog mixed-signal blocks such as bandgap, oscillators, ADCs, DACs, LDOs, and gate drivers
- Knowledge of common tools like Cadence Virtuoso, Maestro, and vManager
- Proficiency in System Verilog, VAMS, or real-number modeling for designing and simulating verification models
- Strong communication and leadership abilities, with the ability to persevere through challenges and drive root-cause analysis to closure
- Strong team-player and self-starter with a "break the part" mentality when troubleshooting
- US citizen or green card holder: This position requires access to documentation that is controlled by the export laws of the United States. Candidates are required to provide proof of either US citizenship, Permanent US residency, or classification as a protected individual as defined in 8USC 1324b(a)(3).
Responsibilities
- Drive the verification of mixed-signal ICs using best practices to ensure first-pass silicon success
- Create and verify block-level models (e.g., System Verilog, VAMS) for use in top-level mixed-mode simulations
- Develop application-specific test benches with automated checkers to evaluate IC functionality and robustness
- Work closely with application, analog design, and digital design leads to verify system-level and IC-level functions and specifications
- Partner with the design team to analyze and address errors found during the verification process
- Foster a collaborative, innovative, and resilient team culture that encourages open communication
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What This Job Offers
Job Type
Full-time
Career Level
Intern
Number of Employees
5,001-10,000 employees
