GPU Physical Design Clocking Engineer

Apple • Austin, TX

74d

About The Position

Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.

Requirements

• Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Exposure to different strategies for clock distribution including balanced trees, mesh, and forwarded clocks.
• Ability to use critical clock metrics revolving around latency, skew, and variation.
• Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
• Understanding of GPU architecture and design units.

Nice To Haves

• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal management.
• Proven track record in solving complex PD and cross functional problems.

Responsibilities

• Collaborate with FE teams to understand chip architecture and drive clocking aspects early in design cycle.
• Drive best in class clocking construction and solutions for performance, power and Area (PPA).
• Collaborate to drive clocking methodologies and 'best known methods' to streamline PD work.
• Come up with guidelines and checklists, drive execution, and supervise progress.
• Communicate and drive the needs of PD and Clocking with multi-functional teams.
• Plan, implement, and analyze high-speed clock distribution networks from the root to leaf.
• Craft test structures to evaluate clocking functionality and performance post Silicon.
• Engage with Test teams pre/post Silicon to debug and analyze problems from a clocking perspective.
• Integrate IP from both internal and external vendors and specify and drive IP requirements in the physical domain.
• Address Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
• Work on large subsystem designs (>20M gates) with frequencies in excess of 1GHz.
• Solve complex PD and cross functional problems, driving results directly or directing a team of engineers.

What This Job Offers

• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees