GPU Logic Design Engineer

Intel • Folsom, CA

128d • $214,730 - $303,140

About The Position

Intel's Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products.

Requirements

• BS+5 Years of relevant industry experience

Responsibilities

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products
• Working with SoC Architecture and platform architecture teams to establish silicon requirements
• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule
• Creating micro architectural specification document for the design
• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs
• Driving vendor's methodology to meet world class silicon design standards
• Architecting area and power efficient low latency designs with scalabilities and flexibilities
• Power and Area efficient RTL logic design and DV support
• Running tools to ensure lint-free and CDC/RDC clean design, VCLP
• Synthesis and timing constraints
• Having achieved multiple tape-outs reaching production with first pass silicon
• Ability to drive and improve digital design methodology to achieve high quality first silicon
• Hands on experience with FPGA emulation, silicon bring-up, characterization and debug
• Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule
• Strong verbal and written communication skills
• Good understanding of verilog and system verilog, synthesizable RTL
• Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis
• Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation
• Background in computer architecture
• Bus fabric, including, but not limited to APB/AHB/AXI
• Power management with multiple power domains, UPF, Power state tables
• Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail
• Knowledge of connectivity tools
• Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers
• Comprehension of asynchronous clock crossing means and methodologies
• Proven track record of bringing logic designs into high volume production
• Ability to work well in a team and be productive under ambitious schedules
• Should be self-motivated and well organized

Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement plans
• Vacation

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees