UIUC Research Park Intern - Functional Safety Hardware

Rivian•Champaign, IL

6h•Onsite

About The Position

Rivian is on a mission to keep the world adventurous forever, building emissions-free Electric Adventure Vehicles and attracting curious, courageous souls. The company constantly challenges what’s possible, reframing old problems and seeking new solutions in unknown areas. The team shares a love of the outdoors and a desire to protect it for future generations. This internship is for Summer 2026 and is optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2028 through May 2028. Active student enrollment is required. Rivian is an equal opportunity employer and does not use graduation dates to determine age or as a basis for discriminatory hiring decisions. If not pursuing a degree, full-time positions are available on the Rivian careers site. Students are responsible for fulfilling any specific university requirements for internship programs. Rivian is seeking a detail-oriented Hardware Functional Safety Engineer to join its engineering team. This role focuses on ensuring next-generation safety-critical systems, specifically High-Performance SoCs and complex PCBs, are robust for real-world deployment. The intern will identify potential failure points through rigorous systematic analysis, ensuring hardware designs are resilient against both random hardware failures and common-cause dependencies.

Requirements

Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
Actively pursuing a degree or one closely related in Electrical Engineering or Computer Engineering
Foundational knowledge of ISO 26262 (specifically Parts 5, 9, and 11)
Understanding of FTA (Qualitative/Quantitative) and the principles of DFA
Ability to read and interpret PCB schematics and understand SoC internal blocks (CPUs, Interconnects, Memory)
A "safety-first" mindset, extreme attention to detail, and the ability to explain complex failure modes to design engineers.

Nice To Haves

Experience with safety analysis tools (e.g., Ansys medini analyze, Item Toolkit, or Reliability Workbench)
Knowledge of ASIL (Automotive Safety Integrity Level) decomposition strategies
Familiarity with hardware description languages (Verilog/VHDL) or hardware verification.
Practical experience with physical layout constraints that impact DFA (e.g., substrate isolation, power domain separation)

Responsibilities

Supporting the functional safety lifecycle for hardware components through quantitative and qualitative analysis.
FTA (Fault Tree Analysis): Support top-down FTA to identify combinations of hardware failures that could lead to a violation of safety goals. You will help build logic trees to visualize and quantify the probability of catastrophic system failures.
DFA (Dependent Failure Analysis): Conduct DFA to identify potential "freedom from interference" issues. You will analyze shared resources (e.g., clock trees, power rails, or physical proximity on a PCB) to identify Cascading Failures and Common Cause Failures (CCF) that could bypass safety redundancies.
FMEDA (Failure Modes, Effects, and Diagnostic Analysis): Assist in performing quantitative FMEDA to calculate hardware architectural metrics (SPFM, LFM) and the Probabilistic Metric for random Hardware Failures (PMHF). You will evaluate the effectiveness of safety mechanisms in detecting or controlling hardware faults.
Design Review: Review hardware requirements and schematics to ensure safety mechanisms (e.g., ECC, parity, redundant paths, voltage monitors) are correctly implemented to mitigate the faults identified in your FTA and DFA.
Documentation: Contribute to the creation of Work Products required by ISO 26262, such as the Hardware Safety Analysis Report and Safety Case fragments.