Full Chip Layout - Physical Architect

Intel • Santa Clara, CA

299d • $186,070 - $262,680 • Hybrid

About The Position

Come join us as a Full Chip Layout - Physical Architect and together let's grow and develop the next leading technology. If you are passionate about pushing the boundaries of technology, we want you on our team.

Requirements

• Bachelor's Degree in Computer/Electrical Engineering or Computer Science with 9+ years of experience, OR Master's Degree in Computer/Electrical Engineering or Computer Science with 6+ years of experience, OR PhD in Computer/Electrical Engineering or Computer Science with 4+ years of experience.
• Experience owning the full chip level and taping out multiple complex SoCs.
• Experience in floor planning, Synthesis, Clocking, Timing Analysis, Place, and route.

Nice To Haves

• Leading the project from all the technical aspects right from Synthesis to Tape-out.
• Supporting the team members in closing any design issues.
• Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens(Mentor), Ansys etc.
• Good understanding of Full-Chip Level Partitioning, Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.
• In-depth understanding on rtl to gds2 flow and understanding of basic device physics.
• Past experience with internal flow development and understand nuances of Physical Design (Structural Design) flow.
• Minimum 2+ years experience with technically leading junior (fresh out of school) to senior/experienced individual contributors.
• Experience with handling developing PDKs (Process Design Kit).
• Working experience with cutting edge technology (5nm or below).
• Very good handle on Tape-out interaction with the foundry and worked on Post-Silicon activities.
• Scripting proficiency in PERL, tcl.
• Own any technical task in SoC physical Design work.
• Documented experience in technically leading past SoC full chip level physical design execution.
• Exposure to various industry standard Physical Design and Sign-Off closure tools.
• Understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.

Responsibilities

• Defines the physical dimensions of the IP or SoC with consideration for overall product costs such as die size optimization, dieperreticle/gooddieperwafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family.
• Establishes the integration plans for disaggregated die with optimization for package and board constraints.
• Performs integration of all dies in a package and completes the relevant checks before tape out.
• Creates and physical database for the IP or SoC.
• Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio.
• Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.
• Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR.
• Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.

Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement plans
• Vacation

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree