Front-End Infrastructure / CAD Engineer (FE Design Verification)

Samsung Electronics America-posted 5 months ago
$144,345 - $257,336/Yr
Full-time • Senior
San Jose, CA
5,001-10,000 employees
Merchant Wholesalers, Durable Goods
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Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

  • Development & Maintenance of Verification Flows: You design, support, and continuously improve highly complex, scalable, and efficient Verification flows, with a focus on ensuring robustness and efficiency.
  • Regression Management & Triage: You lead regression management systems, including flow-based regression support. Proactively manage regression triage, interactive user requirements, and troubleshoot issues to ensure seamless project continuity.
  • Advanced Coverage Analysis: You demonstrate expertise in coverage tools by actively debugging and resolving intricate coverage-related support and merge issues.
  • EDA Tool & Vendor Management: You act as the point of contact for VCS Synopsys issues, providing in-depth debugging, troubleshooting, and solutions to complex problems.
  • RTL Architecture Tool Deployment & Support: You successfully deploy and maintain tools for RTL Architecture, ensuring integration with FE verification flows and addressing any support requirements.
  • Advanced Tool Knowledge & Support: You provide specialized support for various verification tools, including VCS and IES with xprop modeling.
  • Version Control Expertise: You leverage extensive knowledge of Git.
  • 10+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 8+ years of experience with a Master's Degree, or 6+ years of experience with a PhD.
  • Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects.
  • Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues.
  • Familiarity with industry-standard tools including Synopsys VCS, IES, and RTL architecture tools.
  • Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces.
  • Strong communication skills, with experience working directly with EDA vendors to resolve issues and improve tool performance.
  • Ability to work independently and as part of a team, with a proactive approach to problem-solving and a strong attention to detail.
  • medical
  • dental
  • vision
  • life insurance
  • 401(k)
  • free onsite lunch
  • employee purchase program
  • tuition assistance (after 6 months)
  • paid time off
  • student loan program
  • wellness incentives
  • MBO bonus compensation based on performance
  • eligibility for long term incentive plan
  • relocation assistance
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