Front End Design Engineer

Apple • Austin, TX

8h

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather
to do their lives best work. Together we create products and experiences people
once couldn’t have imagined, and now, can’t imagine living without. It’s the
diversity of those people and their ideas that inspires the innovation that runs
through everything we do.

DESCRIPTION

APPLE INC has the following available in Austin, Texas. Design synthesis to
convert functional Register Transfer Level code to digital logic gates in
physical chip design. Conduct formal equivalence to ensure the generation of a
functional design of the chip. Perform Static timing analysis and constraint
development to ensure that the physical design meets timing requirements.
Perform power integrity checks to ensure that the various power domains and
their interfaces are complete. Signoff checks to develop and maintain flows that
help verify the overall quality of the chip designs. Engineer Change Order
implementations to meet the overall functionality and timing closure of the
design. Work with the CAD team and tool vendors to identify and resolve any flow
or integration issues. Create innovative flows and processes to support new chip
designs. Lint checks, to ensure the overall quality of Register Transfer Level
code meets the guidelines. Optimize logic designs to achieve low power, low
area, high performance and timing goals. Generate GDSII file with synthesis,
floor-planning, routing, verification, ECO, and timing analysis. 40 hours/week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
• Experience designing compiler/Genus to generate synthesis netlist.
• Experience in TCL scripting to query or mine data or automate flow ECO implementation for fixing design Power Analysis and techniques to design power saving for the devices
• Using Primetime for timing analysis RTL for understanding the design and making edits Logic equivalent check to ensure the synthesis netlist generated matches the design intent
• Using Innovus and Calibre to implement Physical design, and experience in verification and generating GDSII

Nice To Haves

• N/A

Responsibilities

• Design synthesis to convert functional Register Transfer Level code to digital logic gates in physical chip design.
• Conduct formal equivalence to ensure the generation of a functional design of the chip.
• Perform Static timing analysis and constraint development to ensure that the physical design meets timing requirements.
• Perform power integrity checks to ensure that the various power domains and their interfaces are complete.
• Signoff checks to develop and maintain flows that help verify the overall quality of the chip designs.
• Engineer Change Order implementations to meet the overall functionality and timing closure of the design.
• Work with the CAD team and tool vendors to identify and resolve any flow or integration issues.
• Create innovative flows and processes to support new chip designs.
• Lint checks, to ensure the overall quality of Register Transfer Level code meets the guidelines.
• Optimize logic designs to achieve low power, low area, high performance and timing goals.
• Generate GDSII file with synthesis, floor-planning, routing, verification, ECO, and timing analysis.

What This Job Offers

• Job Type: Full-time