FPGA UVM Verification Engineer- Viasat Government

Viasat, Inc.

10d • Onsite

About The Position

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

Viasat is a rapidly growing technology company that crafts, deploys and operates innovative SATCOM products and services that span the globe! At Viasat Government - Secure Network Systems (SNS) you’ll work with highly motivated engineers in an exciting and dynamic environment. You will be able to use your engineering experience to support the next generation of advanced communications products and systems.

In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for RTL design verification at both the unit and system level, implementing UVM environments and test cases. The individual will collaborate with other engineers from different fields and must be capable of working in both a small team setting and a larger team setting. Experience in the development of high-performance FPGA designs, network encryptors and cryptographic devices is a plus.

Requirements

• Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
• 5+ years FPGA/ASIC design with UVM verification experience
• Foundational knowledge of digital logic and timing considerations
• Strong written and verbal communication skills, ability to work with a geographically distributed team
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
• Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, SoftCore Micro embedments in MicroChip, etc.
• Proven track record to design and implement FPGA/ASIC modules using Verilog and/or VHDL with UVM simulation and testbench development
• Familiarity with designing and coding for re-use, maintainability and scalability
• Desire to a member of a team, collaborating on large system designs
• Work independently, take initiative, and take ownership of tasks and results
• US citizenship required
• Must have an active United States SECRET Clearance
• This is a 100% onsite role and the incumbent will work out of one of these locations: Carlsbad, CA, or Marlborough, MA
• Ability to travel up to 10%

Nice To Haves

• MSEE degree preferred
• Familiarity with TCL, Perl, Python or another scripting language
• Experience with high-speed interfaces like SERDES, DDR2/3/4, LVDS
• Proven experience in debugging, diagnosing, and solving embedded designs issues
• Experience with the rest of the FPGA design process, from the requirements phase to documentation, design, implementation of source code, place & route, testing in hardware, and integration
• Experience and familiarity with Linux-based development environments
• Active United States Secret Security Clearance

Responsibilities

• Testbench development using SystemVerilog/UVM
• Creating drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces
• Writing and debugging constrained random and directed test cases
• Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers
• Collecting and reporting code and functional coverage
• Maintaining regular simulation regressions
• Conduct code and design reviews and participate in multi-functional reviews
• Maintain and control UVM code revision history
• Responsible for owning and driving technical issues to resolution

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees