FPGA Lead – Programmable Logic Designer

Lockheed Martin•Grand Prairie, TX

1d•Hybrid

About The Position

You will be the FPGA Lead – Programmable Logic Designer for Program Strix Indigo. Our team is modernizing a scene generation system to evaluate RF and advanced sensor capabilities, delivering incremental upgrades that expand test fidelity and mission relevance. What You Will Be Doing As the FPGA Lead you will own the end to end development of a sophisticated FPGA based architecture that powers the upgraded scene generation platform. You’ll work hand in hand with software, hardware, and systems engineers to translate system needs into a clean, scalable FPGA solution. Your responsibilities will include: Defining, designing, verifying, and implementing the FPGA architecture using VHDL and/or Verilog. Conducting trade studies to select the optimal FPGA device, balancing logic utilization, power consumption, and thermal performance. Creating detailed FPGA requirements and interface control documents that guide cross functional development. Leveraging AMD Vivado and Altera Quartus toolchains for synthesis, place and route, and timing closure. Applying Universal Verification Methodology (UVM) or equivalent frameworks to build robust testbenches and achieve high coverage verification. Providing technical leadership, mentorship, and code review guidance to junior engineers and interns. Driving the Design Architecture Development process, ensuring milestones are met and risks are mitigated. Collaborating with stakeholders to integrate FPGA outputs with the larger scene generation system, validating performance against RF and sensor test objectives. Why Join Us Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you. We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin’s comprehensive benefits package here. Further Information About This Opportunity: This position is in Dallas. Discover more about our Dallas, Texas location. MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
Experience with the MFC DAR process
Proficiency in VHDL or Verilog programming languages
Experience with Xilinx and Altera FPGAs and the Vivado/Quartus design tool
Experience with FPGA simulation tools and languages such as Synopsys VCS and SystemVerilog
Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
Experience with version control systems, such as Git
Excellent communication, teamwork, and leadership skills

Nice To Haves

Experience with other FPGA vendors, such as Altera or Microchip
Knowledge of software programming languages, such as C, C++, or Python
Experience with debugging and troubleshooting complex digital systems
Knowledge of UVM and experience with UVM-based verification methodologies
Strong analytical and problem-solving skills, with the ability to analyze complex technical issues and develop creative solutions

Responsibilities

Defining, designing, verifying, and implementing the FPGA architecture using VHDL and/or Verilog.
Conducting trade studies to select the optimal FPGA device, balancing logic utilization, power consumption, and thermal performance.
Creating detailed FPGA requirements and interface control documents that guide cross functional development.
Leveraging AMD Vivado and Altera Quartus toolchains for synthesis, place and route, and timing closure.
Applying Universal Verification Methodology (UVM) or equivalent frameworks to build robust testbenches and achieve high coverage verification.
Providing technical leadership, mentorship, and code review guidance to junior engineers and interns.
Driving the Design Architecture Development process, ensuring milestones are met and risks are mitigated.
Collaborating with stakeholders to integrate FPGA outputs with the larger scene generation system, validating performance against RF and sensor test objectives.