FPGA Design Engineer, Senior Staff

d-Matrix•Santa Clara, CA

4d•Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, Master's degree preferred with a Minimum of 5+ years of experience in FPGA design and verification.
Expertise in hardware design using Hardware Description Languages (HDLs) like Verilog or VHDL
Familiarity with RISC-V architecture and embedded systems development
Understanding of hardware-software integration concepts
Experience with scripting languages like Python for test automation
Strong analytical and problem-solving skills
Excellent communication, collaboration, and teamwork abilities
Thrive in dynamic environments where innovative problem-solving is key
Experience with industry-standard management protocols (MCTP, PLDM, SPDM)
Experience with platform BMC (Baseboard Management Controller)
Knowledge of power management techniques (PMBus)
Knowledge of hardware security and secure boot concepts.
Experience with cloud server architectures and concepts

Responsibilities

Design and verify FPGA-based solutions for d-Matrix AI inference accelerator management
Define FPGA microarchitecture specifications and collaborate with stakeholders to ensure alignment with project requirements.
Develop resilient dual boot architecture for multi-core multi chiplet booting
Design and implement hardware and software modules for platform power management, health monitoring, and telemetry data acquisition.
Interface with host server BMC through SMBus mailbox with management protocol overlays such as MCTP, PLDM and SPDM
Integrate RISC-V CPU cores and related firmware into FPGA designs.
Develop eFuse controller within the FPGA
Design and integrate a secure boot solution adhering to NIST standards within the FPGA to enable secure booting of d-Matrix accelerator chiplets
Collaborate with cross-functional teams to ensure seamless hardware-software integration and support inference accelerator hardware bring-up and troubleshooting.
Author Python scripts for hardware testing and automation