FPGA Design Engineer - Early Career

Lockheed Martin•Boulder, CO

3d•$68,000 - $119,830•Onsite

About The Position

By bringing together people that use their passion for purposeful innovation, at Lockheed Martin we keep people safe and solve the world's most complex challenges. Our people are some of the greatest minds in the industry and truly make Lockheed Martin a great place to work. With our employees as our priority, we provide diverse career opportunities designed to propel development and boost agility. Our flexible schedules, competitive pay, and comprehensive benefits enable our employees to live a healthy, fulfilling life at and outside of work. At Lockheed Martin, we place an emphasis on empowering our employees by fostering innovation, integrity, and exemplifying the epitome of corporate responsibility. Your Mission is Ours. Lockheed Martin Space is seeking a full-time Early Career FPGA Design Engineer. This role will be responsible for: · developing an understanding of mission processing code written in C++ and implement for hardware processing. · developing, integrating, and testing of processor subsystem features and interfaces in FPGA hardware. · generating requirements, creating FPGA code, and test bench development. The successful candidate will have experience and/or knowledge of C++ or MatLab, HDL languages, and experience designing with Vivado. Must be a US Citizen; this position will require a government security clearance. This position is in Boulder, Colorado at our offices which have a collaborative and modern agile workspace.

Requirements

Bachelor of Science or higher from an accredited college in Electrical Engineering, Computer Engineering or related discipline, or equivalent experience/combined education.
Ability to obtain a TS/SCI Clearance required for this role.
Understanding of HDL Languages (VHDL & Verilog)
Experience designing with Vivado

Nice To Haves

Proficient in Matlab & C++
Digital logic design experience.
Experience interfacing FPGAs with processors.
Experience with Vitis Model Composer.
Experience with Matlab HDL Coder
Familiarity with Xilinx platforms and tools.
Knowledge of FPGA concepts like clock domains, memory hierarchies, and routing.
Demonstrated experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
Knowledge of space-grade/qualified FPGAs and ASICs.

Responsibilities

developing an understanding of mission processing code written in C++ and implement for hardware processing.
developing, integrating, and testing of processor subsystem features and interfaces in FPGA hardware.
generating requirements, creating FPGA code, and test bench development.