About The Position

Intuitive Machines is seeking a Firmware Engineer Lead specializing in Versal Hardware Acceleration to support the Lunar Terrain Vehicle (LTV) program. The LTV is NASA’s next-generation autonomous lunar rover, and this role will focus on developing and leading RTL firmware and software modules for Xilinx Versal ACAP hardware, enabling hardware-accelerated autonomy, vision, and navigation functions in real time. The successful candidate will work at the intersection of embedded systems, FPGA development, and autonomy software, creating high-performance compute pipelines to process sensor data, support decision-making, and ensure safe rover operations in the lunar environment. Employment in this role is contingent upon NASA selecting Intuitive Machines as a winner of the LTVS program, scheduled for announcement later in 2025.

Requirements

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, Robotics, or related field (Master’s preferred)
  • 8+ years of experience in this domain
  • Experience with hardware-accelerated algorithm design in aerospace, defense, automotive, robotic, AI, quantitative finance or other contexts
  • Experience certifying hardware-accelerated algorithm design for safety-critical and mission-critical applications
  • Familiar with high-reliability software standards (NPR 7150.2D and NASA-STD-8739.8B and NASA CBCS requirements (e.g. SSP 50038))
  • Experience with the AMD Versal architecture strongly desired
  • Experience with Nvidia CUDA architecture strongly desired

Nice To Haves

  • Experience with ROS/ROS2 and integration of hardware acceleration into robotics frameworks
  • Background in computer vision, AI/ML inference (CNNs, SLAM, path planning)
  • Familiarity with radiation-tolerant FPGA design practices for space applications
  • Experience in NASA, defense, or spaceflight programs
  • Knowledge of DO-254, DO-178, or equivalent safety-critical development standards

Responsibilities

  • Understand self-driving algorithm designs as proposed by the software team, able to dissect, critique, and bend designs to fit hardware capabilities
  • Design, implement, and test hardware acceleration algorithms
  • Understand hardware processing capabilities across multiple modalities (CPU, NPU/AIE, GPU, FPGA, ASIC), quantify relative performance, and recommend ways to optimally distribute algorithms across available flight hardware
  • Analyze hardware performance and produce trade studies for hardware selections and software implementation
  • Rigorously verify the design and performance of hardware acceleration algorithms to ensure compliance with applicable NASA CBCS safety requirements
  • Manage a small team working on all aspects of the above, decomposing a large complex problem into individual problems, assigning them out, and monitoring progress towards completion
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