Firmware Engineer III
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About The Position
The Firmware Design Engineer will be responsible for the design, development, documentation, integration, testing, and debugging of FPGA and SoC architecture specifically tailored for Department of Defense (DoD) systems. This role involves integrating firmware designs into compact security devices and network systems, ensuring that all components function seamlessly together. The engineer will engage in various tasks including FPGA/SoC design, simulation, verification, and the generation of design documentation. Additionally, the role requires thorough firmware integration and testing to validate the performance and reliability of the systems being developed. The Mission Solutions and Technologies (MST) business area, where this position resides, is dedicated to providing affordable, turn-key solutions for command/control, communications, integrated ISR (Intelligence, Surveillance, and Reconnaissance), force protection, and security on a global scale. The MST team boasts a rich history of supporting the DoD, Department of Homeland Security, and both commercial and international clients, leveraging years of expertise in platform operations, engineering, and full lifecycle management across various domains including air, land, sea, space, and cyber. The ideal candidate will possess a Bachelor of Science degree in Electrical Engineering or a related engineering discipline, along with a minimum of six years of relevant experience in Electrical Engineering. Proficiency in FPGA design using VHDL, particularly with Xilinx FPGAs/SoCs (Ultrascale+) and development tools such as Vivado and Vitis, is essential. Experience with Altera, MicroSemi, or Cypress FPGAs is also desirable. The role demands a solid understanding of state machine design, high-speed digital bus design (including PCIe, Ethernet, USB, SPI, uSD, I2C, and serial), and the ability to perform static timing analysis for FPGA/SoC designs. Familiarity with scripting languages like Python and Tcl, as well as a foundational understanding of C/C++, is required. Hands-on experience in laboratory settings for hardware bring-up and unit testing of FPGA/SoC designs using standard test equipment is crucial. The candidate should also be adept with integration and debugging tools such as digital multi-meters, power supplies, oscilloscopes, logic analyzers, and protocol analyzers for various communication protocols. Knowledge of interface and design documentation, including functional block diagrams and hardware design specifications, is necessary. The ability to work collaboratively in a multi-functional, interdisciplinary team environment is a must, along with the capability to obtain and maintain a United States Secret Security Clearance.
