FE Design Verification Engineer (FE Infra)

Samsung Electronics•Austin, TX

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities We’re seeking a highly skilled and motivated Sr. Front-End (FE) Design Verification Engineer to join our FE Infrastructure team. The ideal candidate will have experience in FE Design Verification flows, tools, and methodologies. This is a senior level individual contributor role which requires deep technical expertise across multiple verification tools and platforms, as well as a track record of solving complex challenges in FE infrastructure and support. Candidates should possess a specialized skill set that encompasses design verification, regression management, coverage analysis, RTL architecture, tool deployment, and interaction with industry-leading EDA vendors. You design, support, and continuously improve highly complex, scalable, and efficient Verification flows, with a focus on ensuring robustness and efficiency You collaborate with verification teams on advanced flow-based regression tools and maintain them by providing consistent support and updates to meet evolving project demands You own regression management systems, including flow-based regression support, proactively managing regression triage, interactive user requirements, and troubleshooting issues to ensure unified project continuity You ensure compatibility across platforms and resolve any tool-specific issues in support of FE verification workflows You regularly liaise with Synopsys vendors and other EDA partners to coordinate tool support, resolve escalated issues, and stay updated on new developments to ensure high-quality support for verification processes You act as the point of contact for VCS Synopsys issues, providing in-depth debugging, troubleshooting, and solutions to complex problems You debug and resolve complex coverage-related issues, including regression fail triaging and flow stability, while supporting end-to-end coverage analysis workflows to ensure accurate data insights for coverage closure You successfully deploy and maintain tools for RTL architecture, ensuring seamless integration with FE verification flows and addressing any support requirements You provide guidance on RTL architectural workflows and deployment best practices

Requirements

15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects
Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues
Strong understanding of industry-standard tools including Synopsys VCS, IES, and RTL architecture tools
Experience working directly with EDA vendors to resolve issues and improve tool performance
Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces, with an ability to support and streamline versioning workflows
Excellent communication skills, with the ability to work independently and as part of a team, utilizing a proactive approach to problem-solving and a strong attention to detail

Responsibilities

Design, support, and continuously improve highly complex, scalable, and efficient Verification flows, with a focus on ensuring robustness and efficiency
Collaborate with verification teams on advanced flow-based regression tools and maintain them by providing consistent support and updates to meet evolving project demands
Own regression management systems, including flow-based regression support, proactively managing regression triage, interactive user requirements, and troubleshooting issues to ensure unified project continuity
Ensure compatibility across platforms and resolve any tool-specific issues in support of FE verification workflows
Regularly liaise with Synopsys vendors and other EDA partners to coordinate tool support, resolve escalated issues, and stay updated on new developments to ensure high-quality support for verification processes
Act as the point of contact for VCS Synopsys issues, providing in-depth debugging, troubleshooting, and solutions to complex problems
Debug and resolve complex coverage-related issues, including regression fail triaging and flow stability, while supporting end-to-end coverage analysis workflows to ensure accurate data insights for coverage closure
Successfully deploy and maintain tools for RTL architecture, ensuring seamless integration with FE verification flows and addressing any support requirements
Provide guidance on RTL architectural workflows and deployment best practices