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The ESD Engineer at Cirrus Logic is responsible for the development of I/O libraries, focusing on the design, simulation, characterization, and validation of I/O pad libraries. This role involves defining ESD methodologies and specifying ESD requirements at both chip and IP levels, as well as designing ESD protection devices and circuits. The engineer will also develop test structures for characterizing silicon for ESD/LUP properties and will work closely with foundries on ESD library and rule development activities. A holistic understanding of ESD/EOS protection for mixed-signal CMOS circuits is essential to ensure comprehensive strategies without gaps.