Microchip Technology Inc.-posted 2 months ago
$68,640 - $128,000/Yr
Full-time • Entry Level
San Jose, CA
5,001-10,000 employees

Microchip Technology Inc. has a Software Engineer, FPGA Place and Route opening based in San Jose, California. The successful candidate will be responsible for developing new placement and routing algorithms. In this role, you will be working within the Physical Design team of other software engineers delivering high-performance place and route software. Our placement and routing tools are distributed commercially to a wide range of customers and are used internally for the exploration of new FPGA architectures. We research and implement sophisticated approaches for solving gigantic problems – like finding high-quality placements for millions of movable modules, or routing circuits whose graph representations contain hundreds of millions of edges. To do this, we draw from a variety of computer science domains including Machine learning, Graph Neural Network, Numerical optimization, Linear programming, Boolean satisfiability, Hyper-graph Partitioning, Stochastic search, Graph theory, and Traffic routing. You will work closely with other FPGA Software Engineering teams to help deliver a comprehensive software suite for designing Microchip’s FPGAs and managing the entire design flow from entry, to synthesis, through place-and-route, timing, power analysis, and simulation.

  • Develop state-of-the-art FPGA CAD algorithms to improve circuit performance, power, and tool runtime.
  • Execute methodical, scientific experiments to validate the extent of algorithmic improvements.
  • Analyze and share your data with various groups within the company.
  • Perform design reviews, unit testing, and code reviews.
  • Own and maintain code modules.
  • Study literature in the CAD industry and contribute to research discussions.
  • BS, MS or PhD in CS/EE or related field.
  • 0-2 years of relevant research or work experience in programmable architecture, applications implementation, or Software Engineering.
  • Strong knowledge and ability in C++, as well as a deep understanding of algorithms and data structures.
  • Comfortable with software development in a Linux environment.
  • Outstanding oral and written communication skills, willingness to document work products.
  • Exposure to Placement, Routing, Synthesis, Static Timing Analysis (STA) for FPGA or ASIC.
  • Familiarity with PyTorch, Graph Neural Network, CUDA, Machine learning, linear and non-linear optimization.
  • Exposure to parallel programming techniques, like TBB.
  • Experience with source code management systems (Git).
  • Experience with shell scripting languages (Python, TCL, Bash, Perl).
  • Competitive base pay.
  • Restricted stock units.
  • Quarterly bonus payments.
  • Health benefits that begin day one.
  • Retirement savings plans.
  • Industry leading ESPP program with a 2 year look back feature.
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