Engineer, Design Verification Engineering

Analog Devices•Wilmington, MA

23h•$87,188 - $119,906

About The Position

Analog Devices is expanding our team that architects, designs, and verifies Foundational Security Solutions to internal and external customers. This is an excellent opportunity to be part of a growing team with visibility and access across the company’s Business Units developing a wide range of leading-edge IC solutions that require or benefit from Secure HW/FW/SW.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
Typically 2–5 years of experience in digital or mixed‑signal design verification.
Proficiency in SystemVerilog and familiarity with UVM methodology.
Experience with RTL simulation, waveform debug, and EDA verification tools.
Solid understanding of digital design fundamentals, including FSMs, clocking, resets, and basic CDC concepts.
Strong analytical, debugging, and problem‑solving skills.
Ability to communicate technical issues clearly and collaborate across disciplines.

Nice To Haves

Experience verifying security‑related hardware, such as cryptographic accelerators (AES, SHA, RSA, ECC), secure controllers, or root‑of‑trust blocks.
Familiarity with secure boot flows, key storage, authentication mechanisms, and access control concepts.
Knowledge of common interfaces used in SoCs (APB, AHB).
Knowledge of formal verification
Ability to utilize AI Agents or copilot to solve complex problems.
Scripting experience (Python, Perl, or TCL) for verification automation.

Responsibilities

Develop and execute design verification plans based on product requirements and architecture specifications.
Create, enhance, and maintain SystemVerilog / UVM‑based/ C verification environments for block‑level and subsystem‑level verification.
Write and debug directed and constrained‑random tests, checkers, assertions, and functional coverage.
Collaborate closely with design engineers to understand design intent, debug failures, and drive closure of functional and coverage gaps.
Analyze simulation results, identify root causes of issues, and clearly document findings.
Support regression testing, verification sign‑off, and release readiness.
Contribute to methodology improvements, reusable VIP, and best practices within the DV team.
Interface with post‑silicon validation and lab teams to correlate pre‑silicon results and support silicon bring‑up as needed.