Enablement Engineer, On-chip power delivery, Staff

Qualcomm • San Diego, CA

104d • $140,000 - $210,000 • Remote

About The Position

Qualcomm has a position in San Diego, CA, focusing on on-chip power grid optimization for sub 2nm nodes. The role involves driving 3D system integration, balancing performance and cost, and includes responsibilities such as integrated VRs and backside power delivery. Ideal candidates should have a background in 2.5D/3D on-chip integration, process technology, and design enablement.

Requirements

• Master of Science in Electrical Engineering or above
• Deep understanding of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis
• Programming skills, such as Python, Matlab for automation, data analysis, and results summary
• Knowledge of digital design PnR from floorplan stage and IP placement
• Knowledge of digital design PnR flow
• Being familiar with SPICE
• Good communication skills

Responsibilities

• Develop power grid structure for key IPs (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance
• Provide design solutions for IR/EM and routing optimization
• Work with process team for process tuning to achieve better PDN (Power Delivery Network) design
• Support advanced process node PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out
• Provide guidance to PnR (Place and Route) designer on PDN issue fixing
• Drive backside power delivery solution balancing performance and cost

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees