Embedded Adaptive Hardware Engineer

Analog Devices•San Jose, CA

13d

About The Position

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X) . Embedded Adaptive Hardware Design Engineer For more than five decades, Analog Devices (ADI) has transformed how the world senses, measures, and interprets data—from precision analog circuits to advanced mixed-signal SoCs. Today, ADI is increasingly recognized as “the Intelligent Edge company,” leading digital transformation and reimagining the engineer’s journey with AI-driven tools and customer-first design experiences. Looking ahead, ADI is making bold bets to double its presence in industrial automation by 2030 , while accelerating breakthroughs in healthcare, robotics, automotive, and sustainability. ADI’s Embedded FPGA (eFPGA) team within the Digital Business Unit (DBU) plays a pivotal role in this transformation. The team is driving innovation in heterogeneous processing platforms, delivering industry-leading solutions that enable high-speed, real-time hardware adaptability and product differentiation across diverse markets and applications. Through multi-project execution and architectural innovation, the eFPGA team continues to advance this technology as a cornerstone of ADI’s Intelligent Edge strategy. To fuel this growth, we are seeking talented designers who are passionate about soft-logic design and optimization, software–hardware co-design, and building scalable, future-proof architectures for next-generation systems. If you are excited about pushing the boundaries of real-time processing and shaping the future of adaptive hardware, we invite you to join us at the forefront of technological innovation. What you'll be doing : The group is seeking an experienced Embedded Adaptive Hardware Designer to contribute to the development of the eFPGA architecture and softlogic IDE. You do NOT need to be an eFPGA expert yet need to be experienced in digital hardware/architecture design.

Requirements

Master's degree (or equivalent experience) in Electrical Engineering or related fields.
Knowledge of system-level protocols and operations (e.g. AHB, AXI).
Basic understanding of design verification.
Deeply inquisitive and able to use core technical competencies to provide direction on system architecture.
Excellent communication skills required to work well with multi-functional teams (SoC integration, physical-design, software, marketing, etc.)
Strong EE fundamentals, knowledgeable in computer architecture, timing analysis, process variations, statistical error rates and power analysis.

Nice To Haves

5+ years of proven experience in SoC/microarchitecture design and RTL coding.
Tapeout experience in advanced nodes (N4/N5 or similar).
Understanding of functional-safety (FuSA) hardware requirements.
Understanding of chiplet protocols (e.g. UCIe) and characterization/validation methods in post-silicon environment.

Responsibilities

Documenting eFPGA architecture, specifications, user guides, and design process
Upgrading eFPGA architecture and RTL for the advanced features, such as functional safety and ASIL-D automotive qualification.
Performing hardware-software co-design, such as the PPA analysis/optimization and the debug environment.
Developing the softlogic library (a library of RTLs that will be programmed into the eFPGA) as a part of the developer-friendly IDE that will be integrated into ADI’s CodeFusion Studio.
Porting the eFPGA hardware IP to the advanced technology nodes, such as TSMC 16FFC, TSMC N4/N5.
Integrating the eFPGA IP in the chip with the SoC design team.
Interacting with the eFPGA verification and PnR team for design iteration.