DSP Systems Engineering (All Levels)

Marvell Technology

22d•Onsite

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell’s CE DSP Architecture System Modeling team is expanding to support next-generation high-speed SerDes and D2D electrical interfaces operating up to 448 Gb/s per lane, including systems using higher-order PAM modulation. This is a high-impact engineering role where you will develop system-level DSP models, C/C++ algorithm prototypes, simulation frameworks, and silicon-correlation analysis that directly influence architecture, DSP/RTL design, validation, and customer applications. Ideal candidates excel in C/C++ DSP implementation, simulation-level debug, and producing reproducible, data-driven insight. We have multiple openings available, across levels. This position will be in San Diego, on-site. Compensation will be adjusted based on level. What You Can Expect DSP & System-Level Modeling (C/C++) Develop behavioral and functional models of key SerDes and D2D DSP blocks, including adaptation loops, timing recovery, and receiver signal processing functions. Implement DSP algorithms and prototypes in C/C++, with Python for configuration, automation, and visualization. Build parameterized system-level models to support architecture evaluation for SerDes up to 448G. Simulation-Level Debug & Analysis Perform simulation-level analysis across DSP, channel, and system blocks to isolate issues and unexpected behaviors. Reproduce complex edge cases and support other DSP and RTL engineers with algorithm-level root-cause analysis. Correlate silicon/lab observations with system-model predictions to accelerate debug and refinement. System and Channel Modeling Integrate S-parameters, jitter/noise sources, device impairments, and IBIS-AMI elements into unified system simulations. Support and expand scikit-rf-based and ADS-based TDR/TDT/SBR pipelines for channel characterization and documentation. Evaluate higher-order PAM performance under real-world signal integrity constraints. Architecture & Cross-Functional Collaboration Work closely with other DSP engineers to convert conceptual ideas and algorithmic approaches into executable C/C++ models. Provide evidence-backed insights in early-phase development to de-risk DSP and RTL implementations. Silicon Bring-Up & Validation Support Use system models to debug silicon performance gaps, timing issues, equalization behaviors, and adaptation anomalies. Create simulation scenarios that mirror lab conditions to accelerate bring-up. Provide validation and AE teams with modeling-based analysis and recommendations. Automation & Tool Development Develop reusable C/C++ and Python modules for parameter sweeps, batch simulations, data pipelines, and visualization dashboards. Contribute to Marvell’s world class internal system simulator, enabling reproducible modeling workflows across teams.

Requirements

M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Applied Physics, or related field
2–12+ years of industry experience in DSP, high-speed communications, embedded firmware, or system modeling
Strong C/C++ programming background with proven delivery in areas such as: DSP algorithm implementation Embedded/firmware or device-driver development High-performance numerical code
Strong debug skills across models, algorithms, and system layers
Solid understanding of DSP fundamentals, high-speed I/O concepts, and SerDes architectures up to 448G
Proficiency in Python for modeling, automation, and analysis
Data aggregation and analysis with tools like Python pandas, and NumPy
Experience correlating simulation results with lab/silicon measurements
Able to work independently and as a team player in a fast-paced environment, with proactive tendencies, strong communication, and collaborative problem-solving skills

Nice To Haves

Experience with IBIS-AMI model development or integration
Familiarity with COM, StatEye, or similar statistical SerDes modeling frameworks
Experience with Keysight ADS for channel modeling, SI analysis, or DSP blocks
Understanding of mixed-signal impairments (PLL/DLL, jitter/noise modeling)
Experience with DSP-RTL co-simulation or time-interleaved ADC architecture
Background building simulation frameworks used in DSP, RTL, or firmware environments
Experience delivering production utilizing AI tools like Cursor
A portfolio of personal projects highlighting a passion for engineering, software development (in GitHub or other), and AI tools

Responsibilities

Develop behavioral and functional models of key SerDes and D2D DSP blocks, including adaptation loops, timing recovery, and receiver signal processing functions.
Implement DSP algorithms and prototypes in C/C++, with Python for configuration, automation, and visualization.
Build parameterized system-level models to support architecture evaluation for SerDes up to 448G.
Perform simulation-level analysis across DSP, channel, and system blocks to isolate issues and unexpected behaviors.
Reproduce complex edge cases and support other DSP and RTL engineers with algorithm-level root-cause analysis.
Correlate silicon/lab observations with system-model predictions to accelerate debug and refinement.
Integrate S-parameters, jitter/noise sources, device impairments, and IBIS-AMI elements into unified system simulations.
Support and expand scikit-rf-based and ADS-based TDR/TDT/SBR pipelines for channel characterization and documentation.
Evaluate higher-order PAM performance under real-world signal integrity constraints.
Work closely with other DSP engineers to convert conceptual ideas and algorithmic approaches into executable C/C++ models.
Provide evidence-backed insights in early-phase development to de-risk DSP and RTL implementations.
Use system models to debug silicon performance gaps, timing issues, equalization behaviors, and adaptation anomalies.
Create simulation scenarios that mirror lab conditions to accelerate bring-up.
Provide validation and AE teams with modeling-based analysis and recommendations.
Develop reusable C/C++ and Python modules for parameter sweeps, batch simulations, data pipelines, and visualization dashboards.
Contribute to Marvell’s world class internal system simulator, enabling reproducible modeling workflows across teams.