Distinguished Memory PHY Architect

Advanced Micro Devices, Inc•Santa Clara, CA

13h•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture, and delivery of next-generation Memory PHY solutions in advanced CMOS technologies. The focus is on long-term impact: setting technical direction, guiding critical design decisions, and enabling teams to deliver differentiated mixed-signal IP across future SoCs. This position is well suited for technologists who value deep technical ownership, architectural influence, and the ability to leave a lasting technical legacy-without requiring people-management as a primary responsibility. THE PERSON: You are a highly respected engineer or architect known for solving difficult problems and raising the technical bar around you. You bring perspective earned from experience, approach challenges with curiosity and pragmatism, and engage others through thoughtful collaboration rather than authority. You are comfortable operating with ambiguity, influencing across organizations, and contributing at both strategic and hands-on technical levels.

Requirements

Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes.
Experience owning or shaping architecture across multiple successful tape-outs.
Deep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations.
Strong understanding of advanced CMOS technologies and modern design methodologies.
Track record of making sound technical decisions in complex, high-risk design spaces.
Ability to influence without formal authority and collaborate effectively across organizational boundaries.
Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience.
Typically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design.

Responsibilities

Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.
Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.
Drive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.
Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.
Influence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.
Support post-silicon bring-up, validation, characterization, optimization, and product readiness.
Communicate complex technical concepts clearly to senior technical peers, leadership, and stakeholders.
Mentor and advise engineers and architects, contributing to a strong and inclusive technical community.