This job is no longer available
There are still lots of open positions. Let's find the one that's right for you.
As a Display Defect Metrology Engineer, you will play a pivotal role in driving advancements in inline wafer-level defect detection through the development and implementation of state-of-the-art metrology techniques. You will provide technical expertise and strategic direction to the metrology team, fostering a culture of innovation and continuous improvement. This role requires a high level of collaboration with process, integration, yield and device groups and a keen problem-solving mindset. This role is fully onsite in Fremont, CA and in wafer fabrication cleanroom environments. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
