Director of System Validation Engineering

Astera Labs • San Jose, CA

100d

About The Position

Astera Labs is seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems. The role involves understanding the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ connectivity products for Artificial Intelligence and Machine Learning applications. The successful candidate will own the development of a comprehensive validation plan and drive its execution, devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, and report results and specification compliance. Additionally, the role requires engaging with key customers directly to understand their needs and highlight the unique capabilities and performance of Astera Labs’ solutions.

Requirements

• Strong academic and technical background in electrical or computer engineering; a Bachelor's is required, a Master's is preferred.
• At least 12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize multiple tasks and work with minimal guidance.
• Entrepreneurial, open-minded behavior and a customer-focused mindset.
• At least 3 years of experience leading a team in a 'lead by example' manner.
• At least 5 years of hands-on experience with Silicon/System bring-up, validation, and debug experience.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence.
• Strong background in developing bench automation techniques using Python.
• Experience with lab equipment including protocol analyzers and in-circuit debuggers.

Nice To Haves

• Working knowledge of C or C++ for embedded firmware and device drivers.
• Familiarity with PCIe compliance standards and involvement in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization and clock recovery.
• Experience with PAM4 SerDes.

Responsibilities

• Understand the performance and functionality requirements for ICs to enable customers developing Data Center systems.
• Own the development of a comprehensive validation plan and drive its execution.
• Devise test automation of ICs and board products in a data-centric manner.
• Design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers to understand their needs and highlight the capabilities of Astera Labs’ solutions.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 251-500 employees